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HCSXXX
HCSXXX Memory Programming Specification
This document includes the programming specifications for the following devices:
* HCS200 * HCS201 * HCS300 * HCS301 * HCS320 * HCS360 * HCS361 * HCS362 * HCS410 * HCS412 * HCS500 * HCS512 * HCS515
1.2
Program/Verify Mode
The Program/Verify mode for the KEELOQ devices allows programming for all memory locations within the device being programmed. With the exception of the decoders, these pins are also used to verify the memory arrays.
1.0
PROGRAMMING THE HCSXXX
All of the KEELOQ(R) devices are programmed using a serial method. This Serial mode allows KEELOQ devices to be programmed while in users' systems, which increases the flexibility of designing cryptographic encoders, decoders and transponders into electronic systems. While some of the devices are capable of being programmed through wireless communications, the subject of this document is focused on wired programmers that make contact with the KEELOQ products while the components are incircuit or in a programmer socket. Additionally, this programming specification only applies to all KEELOQ devices listed above in all packages. Note: For the purpose of this document, "KEELOQ devices" and "KEELOQ products" refers to all of the components listed above.
1.1
Programming Algorithm Requirements
Depending on the device being programmed, the method for entering Programming mode can be achieved through the use of a combination of logic level signals applied to the programming pins. One or two pins are capable of accepting clock signals, while another pin is dedicated to bidirectional data. These pins are detailed in Table 1-1. Additionally, the programming voltage range for VDD is +5V 10% for all the KEELOQ devices. There is not a requirement to apply high voltages to any of the pins beyond the level of VDD in order to enter the Programming mode. For more details about pin configurations during programming, refer to Table 1-1.
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 1
HCSXXX
Pin Diagrams
PDIP, SOIC
S0 S1 S2 NC
1 HCS200 2 3 4
8 7 6 5
VDD NC PWM
S0 S1 S2 VDDB
1 HCS201 2 3 4
8 7 6 5
VDD STEP DATA VSS
VSS
HCS300/301
S0 S1 S2 S3
1 2 3 4
8 7 6 5
VDD LED PWM VSS
S0 S1 S2 SHIFT
1 HCS320 2 3 4
8 7 6 5
VDD LED PWM VSS
S1 S2 S3/RFEN
2 3 4
7 6 5
HCS360/361
S0
1 HCS362
8
VDD LED/SHIFT DATA VSS
S0 S1 S2 S3
1 2 3 4
8 7 6 5
VDD LED DATA VSS
S0 S1 S2/LED LC1
1 HCS410 2 3 4
8 7 6 5
VDD LC0 PWM GND
S0 S1 S2/RFEN/LC1 LC0
1 HCS412 2 3 4
8 7 6 5
VDD LED DATA GND
VDD EE_CLK EE_DAT MCLR
1 HCS500 2 3 4
8 7 6 5
VSS RFIN S_CLK S_DAT
DS41256A-page 2
Preliminary
2004 Microchip Technology Inc.
HCSXXX
Pin Diagrams (Continued)
PDIP, SOIC
LRNIN LRNOUT NC MCLR GND S0 S1 S2 S3
1 2 3 HCS512 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
RFIN NC OSCIN OSCOUT VDD DATA CLK SLEEP VLOW NC NC VDD S1 S0 MCLR NC 1 2 HCS515 3 4 5 6 7 14 13 12 11 10 9 8 NC NC VSS RF_IN S_CLK S_DAT NC
TSSOP
S2 S3/RFEN VSS DATA
1 2 3 4
8 HCS362 7 6 5
S1 S0 VDD LED/SHIFT
S2/LED LC1 GND PWM
1 2 3 4
8 HCS410 7 6 5
S1 S0 VDD LC0
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 3
HCSXXX
TABLE 1-1:
Device HCS200 HCS201 HCS300 HCS301 HCS320 HCS360 HCS361 HCS362 HCS410 HCS412 HCS500 HCS512 HCS515 Note 1: 2: 3: 4: 5: 6: 7: 8: 9:
PIN DESCRIPTIONS (DURING PROGRAMMING)
Pin Number Power Supply 8 8 8 8 8 8 8 8 8 8 1 14 3 Ground 5 5 5 5 5 5 5 5 5 5 8 5 12 Clock 3 3 3, 4 3, 4 3 3, 4 3, 4 3, 4 3 3 6 12 10 Data 6 6 6 6 6 6 6 6 6 6 5 13 9 Other -- -- -- -- -- 2 2 -- -- -- -- 4 -- (Note 1) (Notes 2, 3, 4, 7, 8) (Notes 5, 6, 8, 9) (Notes 7, 8) (Notes 1) (Notes 2) (Notes 2) (Notes 2) (Notes 2) (Notes 2) (Notes 2) Comments
Sends calibration pulse during ACK periods. VDD pin must be driven low after a Program/Verify cycle. In-circuit programming recommended. Used in conjunction with a Microchip Technology 24LC02B device. MCLR, pin 4, is used to enter Program mode. Must apply external clock source to OSCIN while programming. Requires command byte preceding data packet. Verify function not available. Uses checksum in data packet.
DS41256A-page 4
Preliminary
2004 Microchip Technology Inc.
HCSXXX
2.0 MEMORY MAPPING
The program memory maps for KEELOQ products begin at 0x000 and extend as shown in the tables that follow. As a device is being programmed, the address counter automatically increments to the next word location after receiving a data word. The memory maps for all KEELOQ encoders and transponders were designed so that each word is 16 bits wide. Decoder memory maps are 8 bits wide.
2.1
Encoder Memory Maps
HCS200 12 X 16-BIT EEPROM MEMORY MAP
Mnemonic KEY_0 KEY_1 KEY_2 KEY_3 SYNC Reserved SER_0 SER_1 SEED_0 SEED_1 Reserved CONFIG Description Word 0 (LSb's) of 64-bit crypt key Word 1 of 64-bit crypt key Word 2 of 64-bit crypt key Word 3 (MSb's) of 64-bit crypt key 16-bit synchronization value Set to 0x0000 Word 0 (LSb's) of 32-bit serial number Word 1 (MSb's) of 32-bit serial number Word 0 (LSb's) of 32-bit seed value Word 1 (MSb's) of 32-bit seed value Set to 0x0000 Configuration Word
TABLE 2-1:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B
Word Address
TABLE 2-2:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B
HCS201 12 X 16-BIT EEPROM MEMORY MAP
Mnemonic KEY_0 KEY_1 KEY_2 KEY_3 SYNC Reserved SER_0 SER_1 SEED_0 SEED_1 DISC CONFIG Description Word 0 (LSb's) of 64-bit crypt key Word 1 of 64-bit crypt key Word 2 of 64-bit crypt key Word 3 (MSb's) of 64-bit crypt key 16-bit synchronization value Set to 0x0000 Word 0 (LSb's) of 32-bit serial number Word 1 (MSb's) of 32-bit serial number Word 0 (LSb's) of 32-bit seed value Word 1 (MSb's) of 32-bit seed value Discrimination Word Configuration Word
Word Address
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 5
HCSXXX
TABLE 2-3:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B Note 1:
HCS300 12 X 16-BIT EEPROM MEMORY MAP
Mnemonic KEY_0 KEY_1 KEY_2 KEY_3 SYNC Reserved SER_0 SER_1
(1)
Word Address
Description Word 0 (LSb's) of 64-bit crypt key Word 1 of 64-bit crypt key Word 2 of 64-bit crypt key Word 3 (MSb's) of 64-bit crypt key 16-bit synchronization value Set to 0x0000 Word 0 (LSb's) of 32-bit serial number Word 1 (MSb's) of 32-bit serial number Word 0 (LSb's) of 32-bit seed value Word 1 (MSb's) of 32-bit seed value Set to 0x0000 Configuration Word
SEED_0 SEED_1 Reserved CONFIG
MSb of this word is used for auto-shutoff timer.
TABLE 2-4:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B Note 1:
HCS301 12 X 16-BIT EEPROM MEMORY MAP
Mnemonic KEY_0 KEY_1 KEY_2 KEY_3 SYNC Reserved SER_0 SER_1(1) SEED_0 SEED_1 Reserved CONFIG Description Word 0 (LSb's) of 64-bit crypt key Word 1 of 64-bit crypt key Word 2 of 64-bit crypt key Word 3 (MSb's) of 64-bit crypt key 16-bit synchronization value Set to 0x0000 Word 0 (LSb's) of 32-bit serial number Word 1 (MSb's) of 32-bit serial number Word 0 (LSb's) of 32-bit seed value Word 1 (MSb's) of 32-bit seed value Set to 0x0000 Configuration Word
Word Address
MSb of this word is used for auto-shutoff timer.
TABLE 2-5:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B Note 1:
HCS320 12 X 16-BIT EEPROM MEMORY MAP
Mnemonic KEY_0 KEY_1 KEY_2 KEY_3 SYNC Reserved SER_0 SER_1(1) -- -- Reserved CONFIG Description Word 0 (LSb's) of 64-bit crypt key Word 1 of 64-bit crypt key Word 2 of 64-bit crypt key Word 3 (MSb's) of 64-bit crypt key 16-bit synchronization value Set to 0x0000 Word 0 (LSb's) of 32-bit serial number Word 1 (MSb's) of 32-bit serial number Not used Not used Set to 0x0000 Configuration Word
Word Address
MSb of this word is used for auto-shutoff timer.
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Preliminary
2004 Microchip Technology Inc.
HCSXXX
TABLE 2-6:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B
HCS360 12 X 16-BIT EEPROM MEMORY MAP
Mnemonic KEY_0 KEY_1 KEY_2 KEY_3 SYNC_A SYNC_B Reserved SEED_0 SEED_1 SER_0 SER_1 CONFIG Description Word 0 (LSb's) of 64-bit crypt key Word 1 of 64-bit crypt key Word 2 of 64-bit crypt key Word 3 (MSb's) of 64-bit crypt key 16-bit synchronization value A 16-bit synchronization value B or Seed Value (Word 2) Set to 0x0000 Word 0 (LSb's) of 32-bit seed value Word 1 (MSb's) of 32-bit seed value Word 0 (LSb's) of 32-bit serial number Word 1 (MSb's) of 32-bit serial number Configuration Word
Word Address
TABLE 2-7:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B
HCS361 12 X 16-BIT EEPROM MEMORY MAP
Mnemonic KEY_0 KEY_1 KEY_2 KEY_3 SYNC_A SYNC_B/SEED_2 Reserved SEED_0 SEED_1 SER_0 SER_1 CONFIG Description Word 0 (LSb's) of 64-bit crypt key Word 1 of 64-bit crypt key Word 2 of 64-bit crypt key Word 3 (MSb's) of 64-bit crypt key 16-bit synchronization value A 16-bit synchronization value B or Seed Value (Word 2) Set to 0x0000 Word 0 (LSb's) of 32-bit seed value Word 1 (MSb's) of 32-bit seed value Word 0 (LSb's) of 32-bit serial number Word 1 (MSb's) of 32-bit serial number Configuration Word
Word Address
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 7
HCSXXX
TABLE 2-8:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11
HCS362 18 X 16-BIT EEPROM MEMORY MAP
Mnemonic KEY1_0 KEY1_1 KEY1_2 KEY1_3 KEY2_0 KEY2_1 KEY2_2 KEY2_3 SEED_0 SEED_1 SEED_2 SEED_3 CONFIG_0 CONFIG_1 SERIAL_0 SERIAL_0 SYNC Reserved Description Word 0 (LSb's) of 64-bit crypt key 1 Word 1 of 64-bit crypt key 1 Word 2 of 64-bit crypt key 1 Word 3 (MSb's) of 64-bit crypt key 1 Word 0 (LSb's) of 64-bit crypt key 2 Word 1 of 64-bit crypt key 2 Word 2 of 64-bit crypt key 2 Word 3 (MSb's) of 64-bit crypt key 2 Word 0 (LSb's) of 64-bit seed value Word 1 of 64-bit seed value Word 2 of 64-bit seed value Word 3 (MSb's) of 64-bit seed value Configuration Word (LSb's) Configuration Word (MSb's) Word 0 (LSb's) of 32-bit serial number Word 1 (MSb's) of 32-bit serial number 16-bit synchronization value Set to 0x0000
Word Address
TABLE 2-9:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
HCS500 9 X 8-BIT EEPROM MEMORY MAP
Mnemonic CONFIG KEY0 KEY1 KEY2 KEY3 KEY4 KEY5 KEY6 KEY7 Configuration Word Byte 0 (LSb's) of 64-bit manufacturer key Byte 1 of 64-bit manufacturer key Byte 2 of 64-bit manufacturer key Byte 3 of 64-bit manufacturer key Byte 4 of 64-bit manufacturer key Byte 5 of 64-bit manufacturer key Byte 6 of 64-bit manufacturer key Byte 7 (MSb's) of 64-bit manufacturer key Description
Word Address
TABLE 2-10:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09
HCS512 10 X 8-BIT EEPROM MEMORY MAP
Mnemonic KEY0 KEY1 KEY2 KEY3 KEY4 KEY5 KEY6 KEY7 CONFIG Checksum Description Byte 0 (LSb's) of 64-bit manufacturer key Byte 1 of 64-bit manufacturer key Byte 2 of 64-bit manufacturer key Byte 3 of 64-bit manufacturer key Byte 4 of 64-bit manufacturer key Byte 5 of 64-bit manufacturer key Byte 6 of 64-bit manufacturer key Byte 7 (MSb's) of 64-bit manufacturer key Configuration byte Checksum byte
Word Address
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Preliminary
2004 Microchip Technology Inc.
HCSXXX
TABLE 2-11:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
HCS515 9 X 8-BIT EEPROM MEMORY MAP
Mnemonic CONFIG KEY0 KEY1 KEY2 KEY3 KEY4 KEY5 KEY6 KEY7 Configuration byte Byte 0 (LSb's) of 64-bit manufacturer key Byte 1 of 64-bit manufacturer key Byte 2 of 64-bit manufacturer key Byte 3 of 64-bit manufacturer key Byte 4 of 64-bit manufacturer key Byte 5 of 64-bit manufacturer key Byte 6 of 64-bit manufacturer key Byte 7 (MSb's) of 64-bit manufacturer key Description
Word Address
2.2
Transponder Memory Maps
HCS410 16 X 16-BIT EEPROM MEMORY MAP
Mnemonic KEY_0 KEY_1 KEY_2 KEY_3 DISC CONFIG SER_0 SER_1 SEED_0 SEED_1 SEED_2 SEED_3 USR_0 USR_1 USR_2 USR_3 Description Word 0 (LSb's) of 64-bit crypt key Word 1 of 64-bit crypt key Word 2 of 64-bit crypt key Word 3 (MSb's) of 64-bit crypt key Ext. Config. Word/10-bit Discriminator 16-bit Configuration Word Word 0 (LSb's) of 32-bit serial number Word 1 (MSb's) of 32-bit serial number Word 0 (LSb's) of 64-bit seed value Word 1 of 64-bit seed value Word 2 of 64-bit seed value Word 3 (MSb's) of 64-bit seed value Word 0 (LSb's) of 64-bit user area Word 1 of 64-bit user area Word 2 of 64-bit user area Word 3 (MSb's) of 64-bit user area SYNC
TABLE 2-12:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
Word Address
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 9
HCSXXX
TABLE 2-13:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
HCS412 18 X 16-BIT EEPROM MEMORY MAP
Mnemonic KEY0 KEY1 KEY2 KEY3 SEED0 SEED1 SEED2 CFG/SEED3 CONFIG1 CONFIG2 SER0 SER1 USR0 USR1 USR2 USR3 Description Word 0 (LSb's) of 64-bit crypt key 1 Word 1 of 64-bit crypt key 1 Word 2 of 64-bit crypt key 1 Word 3 (MSb's) of 64-bit crypt key 1 Word 0 (LSb's) of 60-bit seed value Word 1 of 60-bit seed value Word 2 of 60-bit seed value Word 3 of 60-bit seed value/Configuration in top nibble Configuration Word 1 (security options) Configuration Word 2 Word 0 (LSb's) of 32-bit serial number Word 1 (MSb's) of 32-bit serial number Word 0 (LSb's) of 64-bit user area Word 1 of 64-bit user area Word 2 of 64-bit user area Word 3 (MSb's) of 64-bit user area The HCS512 is another device that does not conform to the 2-wire protocol described above. For this device, the MCLR pin is driven high while data is held low. After the minimum setup time has been realized, the clock pin is driven high and then low for a minimum amount of time in order to send the HCS512 a Start condition and complete the Entry mode for the next programming sequence. The associated waveform is detailed in Section 5.0 "Program/Verify Mode Electrical Characteristics". The HCS512 is also the only device that requires a checksum be sent to the target device while it is being programmed. See the Checksum Section in the HCS512 Data Sheet, "KEELOQ(R) Code Hopping Decoder" (DS40151), for details on calculating the checksum. Note: The HCS512 requires an external clock signal for the OSCIN pin. This signal is necessary throughout the Programming mode.
Word Address
2.3
Entering Program Mode
Entering the Program/Verify mode will be dependent upon the type of device in use. Most KEELOQ devices use a serial clock and bidirectional data line to access the chips' memory maps. In order to enter the Programming mode, a Start condition is sent to the target device, where the clock and data lines must be held high and low for specified periods of time. That is, all lines are held low while the clock line is driven high. After a short delay, the data line is driven high. At this point, both lines must remain high for another delay period prior to dropping back to ground. After dropping both lines low and providing another delay, the state machine for the KEELOQ device will enter the Programming mode and begin to wait for data, or depending on the component, a bulk erase is performed on the memory array. For the HCS360 and HCS361 devices, the Programming mode is entered by providing a clock source on the clock line and a Start pulse on the data line, as described in the previous paragraph. However, the difference is with driving the S1 pin, as shown in Figure 5-5. Bit 0 of the data packet must be driven on the S1 pin and kept at that level throughout the programming cycles and through verification.
DS41256A-page 10
Preliminary
2004 Microchip Technology Inc.
HCSXXX
2.4 Bulk Write Device 2.7
2.7.1
Polling Write Cycle
HCS201 AND HCS412
All transponders and encoders are bulk erased and programmed with zeros following the Start condition. The bulk erase/write time frame is specified as TPBW, which is minimally 4.0 ms. After the bulk function is complete, the programming state machine continues into the Program mode where it begins to wait for data and clock signals.
2.5
Serial Program/Verify Operation
For all of the encoders and transponders, the memory maps have been designed to be in 16-bit format, which means that each address location contains 16 bits of information including "don't care" bits that are read as zeros. Details relating to the designated pins for clock and data signals are outlined in Table 1-1. The decoders, on the other hand, were designed with memory maps in 8-bit format, so they are discussed separately in the next couple of paragraphs. For specific information relating to the size of the memory maps for a given family of devices, be sure to review the tables in Section 2.1 "Encoder Memory Maps". The following paragraphs were written with the assumption that the target device has been placed into the Programming mode and is now waiting for data or a command byte to continue programming the memory array.
Once the 16th clock cycle for the data word has been generated and the next minimum low time for the clock passes, the clock pin can be driven high to poll the completion of the write cycle. Before the write cycle is complete, the data pin for the target KEELOQ device will be low. After the write cycle is complete, the data pin on the HCS201 and the HCS412 will begin to provide pulses to the programmer in order to signal the completion of the write cycle. As a result, the programmer data pin should be set to high-impedance (input) so that it can read the pulses. After reading the pulses on the data pin, the programmer should drive the clock pin low and make the data pin an output so that data can continue to be driven into the target device. These pulses can be used for calibration sequences for the HCS201 and the HCS412. For information relating to oscillator calibration refer to Section 5.0 "Program/Verify Mode Electrical Characteristics", which discusses oscillator tuning. If the programmer polls the target device for the end of a write cycle, these two devices will continue to emit calibration pulses until their clock lines are driven low. In order to measure the calibration pulses, the clock pin must be driven high prior to the end of the write cycle, otherwise the calibration pulses will not appear.
2.7.2
ALL OTHER KEELOQ DEVICES
2.5.1
ENCODERS/TRANSPONDERS
To input data to the target KEELOQ encoder or transponder, 16 clock cycles are applied to the clock pin of the target device while data is driven into the data pin. Data is clocked into the target device on the falling edge of the clock signal. Also, the minimum high time and low time for the clock signals are 50 s. During verification, data must be sampled on the rising edge of the clock.
2.5.2
DECODERS
Once the 16th clock cycle for the data word has been generated for any of the encoders or transponders or the last clock cycle for a decoder data packet is generated, the clock pin can be driven high to poll for the completion of the write cycle. Before the write cycle is complete, the data pin for the target KEELOQ device will be low. As a result, the programmer data pin should be set to high-impedance (input) so that it can sense the rising edge of data. After the write cycle is complete, the data pin will be driven high until the clock line is driven low again.
To input data to the target KEELOQ decoder, 8 clock cycles are applied to the clock pin of the target device while data is driven into the data pin. Data is clocked into the target device on the falling edge of the clock signals. Also, the minimum high time and minimum low time for the clock signals are 50 s. For the decoder family, there are no verification functions.
2.6
Begin Programming
Write cycles are performed a bit-at-a-time throughout the entire programming sequence for KEELOQ products. The total write cycle, which includes internal processing and programming time, is specified to take a minimum of 50 ms. As a result, programmers can include a delay for the minimum write cycle time or they can poll the target device as discussed in Section 2.7 "Polling Write Cycle".
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 11
HCSXXX
2.8 Verify Mode
4.0
OSCILLATOR TUNING
In terms of verify operations, all KEELOQ encoders and transponders incorporate a security feature that only allows one verify operation to be completed, and it must be completed at the end of the programming sequence before exiting the Programming mode. When implementing polling routines to sense the end of the last write cycle and after driving the clock line low, the programmer can begin to read data by continuing to provide clock cycles to the target device. Note that there is not an Acknowledge bit from KEELOQ devices during the Verify mode. In the case where the programmer provides a time delay to allow for write cycle completion, the programmer can provide clock cycles after the delay to begin reading data. Note: Decoders do not incorporate a verify function.
Calibrating the oscillator of select devices can be completed a number of ways. For the purpose of this document, calibration will be completed using the TwoPoint Calibration Algorithm, which is described in Application Note AN824, "KEELOQ(R) Encoders Oscillator Calibration" (DS00824). The algorithm is as follows: OSCCAL = -8 Program target device Measure oscillator frequency FHIGH OSCCAL = +7 Program target device Measure oscillator frequency FLOW Interpolate: - OSCCAL = 16*(FIDEAL - FLOW)/(FHIGH - FLOW) * Program target device For a better understanding of how to implement this algorithm, the following flow charts are being provided: * * * * * * *
3.0
CONFIGURATION WORD
For detailed descriptions of bit functions for the configuration words of the KEELOQ devices, be sure to download the latest Data Sheet for the respective device from the Microchip Technology web site (www.microchip.com). Configuration word architectures are also shown earlier in Section 2.0 "Memory Mapping".
DS41256A-page 12
Preliminary
2004 Microchip Technology Inc.
HCSXXX
FIGURE 4-1: HCS201 AND HCS412 OSCILLATOR TUNING
Preload Datastream with 0x7 for OSCCAL(1)
Store Average Value as FLOW
Interpolate OSCCAL
Preload Datastream with 400 s Time Element
Measure Calibration Pulses as Time Elements
Reset Target(2)
Program Target
Poll Target for End of Write Cycle
Preload Datastream with Interpolated OSCCAL
Reset Target(2)
Program First Word of Target
Preload Desired Baud Rate
Preload Datastream with 0x8 for OSCCAL(1)
Reset Target(2)
Program Target
Preload Datastream with 400 s Time Element
Program Remaining Target
Program First Word of Target
Store Average Value as FHIGH
Poll Target for End of Write Cycle
Measure Calibration Pulses as Time Elements
Note 1: -8d = 0x7, and +7d = 0x8 2: Cycle Power
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 13
HCSXXX
FIGURE 4-2: HCS362 AND HCS410 OSCILLATOR TUNING
Preload Datastream with 0x7 for OSCCAL(1)
Store Average Value as FLOW
Interpolate OSCCAL
Preload Datastream with 400 s Time Element
Measure Preamble Time Elements
Preload Datastream with Interpolated OSCCAL
Program Target Device
Activate Button Input on Target
Preload Desired Baud Rate
Reset Target(2)
Reset Target(2) Program Target
Activate Button Input on Target
Program Target Device
Measure Preamble Time Elements
Preload Datastream With 400 s Time Element
Store Average Value as FHIGH
Preload Datastream With 0x8 for OSCCAL
Reset Target(2)
Note 1: -8d = 0x7, and +7d = 0x8 2: Cycle Power
DS41256A-page 14
Preliminary
2004 Microchip Technology Inc.
HCSXXX
KEELOQ devices that are capable of oscillator tuning include the HCS201, HCS362, HCS410 and the HCS412. Though, only the HCS201 and HCS412 transmit calibration pulses when polling the chips at the end of write cycles. The other two devices must be tuned according to the preamble pulses that they transmit at the beginning of a data packet. For the best accuracy, use multiple time elements to achieve an average time element value. Typically, a number that is a power of 2n is used in order to simplify the resultant quotient (i.e., 4 or 8). In order to obtain the most accurate time element measurement, the widest possible baud rate should be chosen. For simplifying the two flow diagrams below, a common time element was chosen to the devices that share algorithms. The HCS362 and the HCS410 oscillator tuning register can also be tuned as shown in the algorithm above, but with the caveat that after the device is programmed, the programmer must activate the target device in order to measure the time element in the communication preamble. A typical preamble is shown in Figure 4-3.
FIGURE 4-3:
TE TE
PWM CODE WORD TRANSMISSION TIMINGS
TE TE TE
Preamble = 23 TE
Header = 10 TE
bit 0
bit 1
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 15
HCSXXX
4.1 Programming Flow Charts
PROGRAMMING FLOW CHART 1
Start
FIGURE 4-4:
FIGURE 4-5:
PROGRAMMING FLOW CHART 2
Start
Set VDD = 5.0V 10%
Set VDD = 5.0V 10%
Send Start Sequence
Send Start Sequence
Device Bulk Erase
If Data Bit 0 = 0 Then S1 = 0 Else S1 = 1 Load 16 Bits of Data (LSb first) Load 16 Bits of Complemented Data (LSb first) Wait TWC or Poll Calibration Pulse
Load 16-Bits of Data
Wait TWC or Poll Rising Pulse
No
All Locations Programmed? Yes Begin Verify
No
All Locations Programmed? Yes Begin Verify
Read 16-Bits of Data
Read 16-Bits of Data All Locations Verified? Yes Program/Verify Complete Note: Applies to HCS200, HCS201, HCS300, HCS301, HCS320, HCS362, HCS410 and HCS412 only. No
All Locations Verified? Yes Program/Verify Complete Note:
No
Applies to HCS360 and HCS361 only.
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Preliminary
2004 Microchip Technology Inc.
HCSXXX
FIGURE 4-6: PROGRAMMING FLOW CHART 3
Start
FIGURE 4-7:
PROGRAMMING FLOW CHART 4
Start
Set VDD = 5.0V 10%
Set VDD = 5.0V 10%
Raise NMCLR
Send Start Sequence
Send Start Sequence
Load 8-Bits of Data
Load 8-Bits of Data
No
All Locations Loaded? Yes
No
All Locations Loaded? Yes Load Checksum
Wait TWC or Poll Rising Pulse
Program Complete
Wait TWC or Poll Rising Pulse
Note:
Applies to HCS500 and HCS515 only.
Program Complete
Note:
Applies to HCS512 only.
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 17
HCSXXX
5.0
5.1
PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
Timing Requirements for Program/Verify Mode - Encoders
Standard Operating Conditions (unless otherwise stated) Operating Temperature +25C 5C Operating Voltage 4.5V VDD 5.5V Min 50 50 30 0 -- 4.0 3.5 50 4.0 3.5 50 800 800 50 50 18 0 -- 4.0 4.0 50 100 4.0 2.0 50 9.0 0 50 50 30 0 -- 50 Max -- -- -- -- 30 -- -- -- -- 4.5 -- -- -- -- -- -- -- 30 -- -- -- -- -- 5.0 -- -- 4.0 -- -- -- -- 30 -- Units s s s s s ms ms s ms ms ms s s s s s s s ms ms s s ms ms ms ms ms s s s s s ms Conditions/Comments
AC/DC CHARACTERISTICS
Sym TCLKH TCLKL TDH TDS TDV TPBW TPH1 TPH2 TPROG TPS TWC HCS201 TACKH TACKL TCLKH TCLKL TDH TDS TDV TPBW TPH1 TPH2 TPHOLD TPROG TPS TWC T1 T2 TCLKH TCLKL TDH TDS TDV TWC
Characteristics Clock high time Clock low time Data hold time Data setup time Data out valid time Bulk Write time Hold Time 1 Hold Time 2 Program delay time Program mode setup time Program cycle time Data out valid time Data hold time Clock high time Clock low time Data hold time Data setup time Data out valid time Bulk Write time Hold Time 1 Hold Time 2 Hold time Program delay time Program mode setup time Program cycle time Hold Time 1 Program mode setup time Clock high time Clock low time Data hold time Data setup time Data out valid time Program cycle time
HCS200, HCS300, HCS301, HCS320 and HCS362
HCS360, HCS361
DS41256A-page 18
Preliminary
2004 Microchip Technology Inc.
HCSXXX
5.2 Timing Requirements for Program/Verify Mode - Transponders
Standard Operating Conditions (unless otherwise stated) Operating Temperature +25C 5C Operating Voltage 4.5V VDD 5.5V Min 100 50 50 20 20 -- 4 100 2.2 3 36 Max -- -- -- -- -- 20 -- -- -- 5 -- Units s s s s s s ms s ms ms ms Conditions/Comments
AC/DC CHARACTERISTICS
Sym HCS410, HCS412 TAS TCLKH TCLKL TDH TDS TDV TPH1 TPH2 TPROG TPS TWC
Characteristics ACK start time Clock high time Clock low time Data hold time Data stable time Data valid time Program Hold Time 1 Program Hold Time 2 Bulk write time Program mode setup time EEPROM write time
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 19
HCSXXX
5.3 Timing Requirements for Program/Verify Mode - Decoders
Standard Operating Conditions (unless otherwise stated) Operating Temperature +25C 5C Operating Voltage 4.5V VDD 5.5V Sugg. Value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- * 100 100 100 50 * 100 100 100 100 -- 20 20 -- -- 14 0.015 -- 20 -- 1 0.05 0.05 8 0.05 1 30 20 20 10 14 0.005 10 20 20 10 Min Max Units Conditions/Comments
AC/DC CHARACTERISTICS
Sym HCS500 FCLK TACK TADDR TCLKH TCLKL TCMD TDATA TDS TREQ TRESP TSTART HCS512 TACK TACKH TCLKH TCLKL TPH1 TPH2 TPS HCS515 TACK TCLKH TCLKL TDATA TDS TREQ TRESP TSTART TWTH TWTL *
Characteristics
Clock frequency Decoder acknowledge time Address validate time Clock high time Clock low time Command validate time Command last bit to data first bit Data hold time Command request time Acknowledge time Command request to first command bit Acknowledge time Acknowledge duration Clock high time Clock low time Hold Time 1 Hold Time 2 Program mode setup time Command acknowledge time Clock high time Clock low time Command last bit to data first bit Data hold time Command request time Acknowledge time Command request to first command bit Acknowledge respond time Clock low to next command Depends on decoder status.
500
25000 30 10 1000 1000 10 10 -- 500 1 1000 80 -- 320 320 128 320 64 240 1000 1000 1000 1000 500 1000 1000 1000 --
Hz s s s s s s s ms ms s ms s s s ms s ms ms s s s s ms s s s s FOSC = 4 MHZ FOSC = 4 MHZ FOSC = 4 MHZ FOSC = 4 MHZ FOSC = 4 MHZ FOSC = 4 MHZ FOSC = 4 MHZ
DS41256A-page 20
Preliminary
2004 Microchip Technology Inc.
HCSXXX
5.4 Programming Waveforms (HCS200, HCS300, HCS301, HCS320, HCS362)
PROGRAMMING WAVEFORMS
TPBW TCLKH S2 (Clock) TPS PWM (Data) TPH1 TDH TCLKL bit 0 bit 1 bit 2 bit 3 bit 14 bit 15 bit 16 bit 17 TWC TDS TAS
FIGURE 5-1:
Enter Program Mode
TPH2
Data for Word 0 (KEY_0) Repeat for each word (12 times) Ack Pulse
Data for Word 1 (KEY_1)
Note 1: Unused button inputs to be held to ground during the entire programming sequence.
FIGURE 5-2:
VERIFY WAVEFORMS
Beginning of Verify Cycle Data from Word 0 TWC
End of Programming Cycle
S2 (S3) (Clock) PWM (Data) bit 190 bit 191 bit 0 bit 1 bit 2 bit 3 TDV bit 14 bit 15 bit 16 bit 17 bit 190 bit 191
Note: If a Verify operation is to be done, then it must immediately follow the Program cycle.
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 21
HCSXXX
5.5 Programming Waveforms (HCS201)
PROGRAMMING WAVEFORMS (HCS201)
TCLKH TDS S2 (Clock) TPS TPH1 DATA (Data) TPH2 TCLKL TDH bit 14 bit 15 TWC Ack TACKL TACKH Ack Ack bit 16 bit 17 Data for Word 1 Initiate Data Polling Here TCLKL TPHOLD
FIGURE 5-3:
Enter Program Mode
TPBW
bit 0 bit 1 bit 2 bit 3
Write Cycle Complete Here Repeat for each word (12 times)
Calibration Pulses
Note:
S0 and S1 button inputs to be held to ground during the entire programming sequence.
FIGURE 5-4:
VERIFY WAVEFORMS
Beginning of Verify Cycle Data from Word 0
End of Programming Cycle
DATA (Data) bit 190 bit 191 TWC S2 (Clock) Ack bit 0 bit 1 bit 2 bit 3 TDV bit 14 bit 15 bit 16 bit 17 bit 190bit 191
Note:
If a Verify operation is to be done, then it must immediately follow the Program cycle.
DS41256A-page 22
Preliminary
2004 Microchip Technology Inc.
HCSXXX
5.6 Programming Waveforms (HCS360, HCS361)
PROGRAMMING WAVEFORMS
Acknowledge Pulse TWC bit 14 bit 15 bit 0 bit 1 bit 2 bit 3 TCLKH bit 14 bit 15 bit 16 bit 17
FIGURE 5-5:
Enter Program Mode DATA (Data) T2 S2/S3 (Clock) T1 S1 TDS bit 0 of Word 0 Data for Word 0 (KEY_0) Repeat for each word Note 1: Unused button inputs to be held to ground during the entire programming sequence. The VDD pin The VDDtaken to ground after a program/verify cycle. 2: must be pin must be taken to ground after a Program/Verify cycle.
bit 0 bit 1 bit 2 bit 3 TCLKL TDH
Data for Word 1
FIGURE 5-6:
VERIFY WAVEFORMS
Beginning of Verify Cycle Data from Word0
End of Programming Cycle
DATA (Data) bit 190 bit 191 TWC S2/S3 (Clock) S1 Ack bit 0 bit 1 bit 2 bit 3 TDV bit 14 bit 15 bit 16 bit 17 bit 190 bit 191
Note
1:
A Verify sequence is performed only once immediately after the Program cycle.
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 23
HCSXXX
5.7 Programming Waveforms (HCS410, HCS412)
PROGRAMMING WAVEFORMS
TPBW TCLKH S2 (Clock) TPS PWM (Data) TPH1 TDH TCLKL bit 0 bit 1 bit 2 bit 3 bit 14 bit 15 bit 16 bit 17 TWC TDS TAS
FIGURE 5-7:
Enter Program Mode
TPH2
Data for Word 0 (KEY_0) Repeat for each word (18 times) Ack Pulse
Data for Word 1 (KEY_1)
Note
1: 2:
Unused button inputs to be held to ground during the entire programming sequence. The VDD pin must be taken to ground after a Program/Verify cycle.
FIGURE 5-8:
VERIFY WAVEFORMS
Beginning of Verify Cycle Data from Word 0 TWC
End of Programming Cycle
S2 (S3) (Clock) PWM (Data) bit 206 bit 207 bit 0 bit 1 bit 2 bit 3 TDV bit 14 bit 15 bit 16 bit 17 bit 206 bit 207
Note: If a Verify operation is to be done, then it must immediately follow the Program cycle.
DS41256A-page 24
Preliminary
2004 Microchip Technology Inc.
HCSXXX
5.8 Programming Waveforms (HCS500)
PROGRAMMING WAVEFORMS FIGURE 5-9:
TCLKL TPP1 TPP3 TCLKH
TCMD
TADDR
TDATA
TDATA
TACK TWT2
TDS
CLK
C Data TPP2 TPP4
LSb
MSb
LSb
MSb
MSb
LSb
MSb TAW
Decoder Data Start Command A B Command Byte C Configuration Byte Least Significant Byte D E Most Significant Byte F G Acknowledge H
5.9
Programming Waveforms (HCS512)
PROGRAMMING WAVEFORMS
FIGURE 5-10:
MCLR TPS CLK (Clock) TPH1 TPH2
TCLKL TCLKH TACK TACKH
DAT (Data) bit 0 bit 1 bit 78 bit 79 Ack
Enter Program Mode
80-bit Data Package
Acknowledge pulse
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 25
HCSXXX
5.10 Programming Waveforms (HCS515)
PROGRAMMING WAVEFORMS
TCLKL TREQ CLK TSTART TCLKH TDS TDATA TDATA TDATA TDATA TACK TWTH
FIGURE 5-11:
C Data TRESP HCS515 Data Start Command A Note: B
LSb
MSb
LSb
MSb
LSb
MSb
LSb
MSb
TWTL
Command Byte C
Configuration Byte D
LSb E F
MSb G
Acknowledge H
The programming command consists of the following: * * * * * Command Request Sequence (A to B) Command Byte (B to C) Configuration Byte (C to D) Manufacturer's Code Eight Data Bytes (D to G) Activation and Acknowledge Sequence (G to H)
DS41256A-page 26
Preliminary
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 27
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westford, MA Tel: 978-692-3848 Fax: 978-692-3821 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
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ASIA/PACIFIC
India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 Japan - Kanagawa Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459
EUROPE
Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 France - Massy Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Ismaning Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 England - Berkshire Tel: 44-118-921-5869 Fax: 44-118-921-5820
10/20/04
DS41256A-page 28
Preliminary
2004 Microchip Technology Inc.

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